1. Field of the Invention
The present invention relates to a semiconductor device including an ESD protection element. In particular, the present invention relates to an ESD protection element of an off transistor type provided between an external connection terminal and an internal circuit region, for protecting an internal element configured to operate at low voltage in the internal circuit region from destruction caused by ESD.
2. Description of the Related Art
In semiconductor devices, which are also called ICs, the following phenomenon is known in which discharge current flows in a device due to electrostatic discharge (hereinafter referred to as “ESD”), resulting in destruction of the device caused by the onset of local heat generation or an electric field concentrates. Then, in order to prevent destruction caused by ESD, an ESD protection element is generally provided between an external connection pad and an internal circuit region.
It is known that an N-type MOS transistor (hereinafter abbreviated as “NMOS”) in a so-called off state, in which potential of the gate electrode is fixed to a ground potential, is used as the above-mentioned protection element for a semiconductor device including MOS transistors. Such an NMOS is referred to as an off transistor.
In the following description, a P-type MOS transistor is described as well. The P-type MOS transistor is abbreviated as “PMOS”.
A drain electrode of the above-mentioned off transistor is connected to the external connection PAD while the off transistor is used, and hence the off transistor is required to have a drain withstand voltage that is equal to or higher than the operating voltage of the IC. Meanwhile, the drain withstand voltage is also required to be lower than the withstand voltage of an element used in the internal circuit region, which is typified by a transistor, in order to prevent an ESD surge from reaching the internal circuit region.
Since the drain withstand voltage of the off transistor is determined by a so-called surface breakdown which is an avalanche breakdown that occurs when a depletion layer is not sufficiently extended in a drain region because the gate electrode is off, and by a so-called junction breakdown which is an avalanche breakdown that occurs at a PN junction between the drain region and a well region fixed to the ground potential or an element isolation region, taking those two types of breakdown into consideration the withstand voltage is set to a value that is equal to or higher than the operating voltage of the IC and lower than the withstand voltage of a device used in the internal circuit region.
The starting voltage for the above-mentioned surface breakdown is determined mainly by the thickness of a gate oxide film and the concentration and length of a low-concentration drain extension region. The starting voltage for junction breakdown is determined by the concentration of a high-concentration drain region and the concentrations of a well and an element isolation region.
Here, in low voltage operation ICs configured to operate at 8 V or lower, in order to reduce manufacturing cost, the thickness of a gate insulating film and the concentrations of a drain region and a well are not set individually between a device used in an internal circuit region and an ESD protection element. As a result, although the ESD protection element is supposed to have a lower withstand voltage than the device used in the internal circuit region, it is difficult to achieve such a difference in withstand voltage, with the result that the IC cannot be protected by the ESD protection element.
In view of the above, the following measures are taken in the related art. One of the measures involves increasing the concentration of a channel region through ion implantation into the channel region, for example, such that the channel region has a high concentration, thereby reducing the withstand voltage of the ESD protection element, and another involves devising a circuit configuration (for example, see Japanese Patent Application Laid-open No. 2011-124285).
However, in the case of taking the measure involving implanting ions into the channel region, even when high concentration ion implantation is performed before a gate insulating film is formed, a Si surface is damaged by asking necessary to remove a cured resist. As a result, the life time of the gate insulating film is shortened. On the other hand, even when high concentration ion implantation is performed after the gate insulating film is formed, ions are directly implanted into the gate insulating film, and the lifetime of the gate insulating film is consequently shortened. In addition, a dedicated mask is necessary, leading to an increase in manufacturing cost and TAT, which indicates how long it takes to produce one product.
Further, in the case of taking an ESD protection measure such as the one in Japanese Patent Application Laid-open No. 2011-124285 described above, the circuit scale increases.